We use an expand Editor to make the Binary data file that is requested by the Logic simulator ...
To call the expand editor TEXP type :
" texp component_name [ext_do_file [par1 [par2 ...]] "
component_name : name of your component ( directory )
ext_do_file : file to automatically executed commands ( option ) .
par1 , par2 : external variable used for commands ( option ) .
The Turbo Expand editor TEXP can Expand HIERARCHICAL electronic schemas and can use to edit it :
* control the "DEPTH" of expand by using the command "PRIMitive" , the parameters defining name and value of properties that are on the body of a primitive ( the expand stops at that level )
* store in the design file , in the order you mentionned , the properties ( name , values ) that belong to object :
** instance body
** instance pin
** net
** frame .
* View the expanded sheet , select object , get status ... etc .
* View down into instance sheet , until you reach the bottom level , view up until you reach the top level .
* view another sheet or symbol .
* change menu or key function
* define the time step that will be used during logic simulation and to convert before to store the "TIME" properties ( with the command "TIME STEP" ) .
* show the owner of selected properties using the command "SHOW LINK" .
* You can generate a ASCII file DATA to get design data ( for netlist , customised tools , ... ) using the command GENerate DATa .
-> Logic Simulator : "tsim"
For logic simulation , we use the logic simulator "tsim" ...
It use a logic Matrix for (States,values,forces) ...
It allows 4 Spikes models : Nosuppress , supress , Igen , Pessimistic ...
It take into account also Propagation delays ....
It may generates Warnings for timings : setup , hold , Min-pulse ...
You may interactively see your schematic, put probes at each levels ...etc
To call the LOGIC SIMULATOR "TSIM" type :
`` tsim component_name [ MIn / TYp / MAx [ ext_do_file [ file_type [ par1 [ par2...]]]] ``
component_name : name of your component ( directory )
MIn / TYp / MAx : timing , delays switches ( option ) .
ext_do_file : file to automatically executed commands ( option ) .
file_type : extension to find the expanded file ( option ) .
par1 , par2 : external variable used into ext_do_file ( option ) .
The Turbo logic simulator can simulated HIERARCHICAL electronic schemas and can use to simulate it :
* symbols created with the symbol editor TSED
* sheets created with the sheet editor TNED
* design file created with the sheet expander TEXP
* MATRICE of LOGIC STATES :
** LEVELS : "I" ,"0" , "X" , "1"
"X" : unknown
"I" : indeterminate
** STRENGTHS : "S" , "W" , "R" , "Z" , "U"
"S" : Strong
"W" : Weak
"R" : Resistive
"Z" : high impedance
"U" : Undefined state .
* you can make and use your OWN BEHAVIOURAL MODELS
* SYMBOL , SHEET that can be VIEWED , SELECTED ...
* SELECT AREA , ... , AND SELECT PROPERTIES with "WILD CHAR" (*) .
* INIT , DEFINE ( function of time ) , all equipotentials by their names , using commands as : FORCE , CLOCK PERIOD , "INIT" properties on "NETS" , "GLOBAL" name .
* LIST , TRACE the results of simulation : using commands : LIST , TRACE , PERIOD LIST , PERIODE TRACE
* define a name for UN_NAMMED EQUIPOTENTIAL using : PROBE ( at level 0 , or -1 , -2 ... using VIEW DOWN )
* regenerate the simulation with new equipotential .
* view the expanded sheet , select object , get status ... etc .
* view down into instance sheet , until you reach the bottom level , view up until you reach the top level .
* view another sheet or symbol ( VIEW SHEET ) .
* view UP , DOWN , to see and PROBE signals into sheet .
* execute automatic SCRIPT ( DO ).
* define BREAK time point for a wanted time and NET state .
* reset action : using FORGET ... , RESET SIM TIME
* define a "SPIKE MIN" under this value no warning for spike condition ( control only the WARNING messages , and so allows to suppress the unwanted warning message , for instance during an init period , or when spikes are too short to be significant )
* define 4 different SPIKE strategies ( SPIKE MODel ) .{Nosuppress/Suppress/Igen/Pessimistic}
* define , if needed, for some (or all) "INSTANCES" (and their child recursively ) , their own switches : "Min / Typ / Max" ( TIMING INDex ) , interactively during logic simulation .
* define coefficients to modify delays , timings (Setup, Hold, Minpulse ) using TIMING COEFFICIENT , interactively during logic simulation .